New structures of the concurrent error detection systems for logic circuits
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Publication:2397271
DOI10.1134/S0005117917020096zbMath1362.94072OpenAlexW2586174556MaRDI QIDQ2397271
D. V. Efanov, V. V. Sapozhnikov, V. V. Dmitriev, Vl. V. Sapozhnikov
Publication date: 22 May 2017
Published in: Automation and Remote Control (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1134/s0005117917020096
areaduplicationrealization complexityinformation vectorparity codeberger codecode with summation of weighted transitionsconcurrent error detection systemoptimal code with summation
Related Items (2)
Synthesis of self-checking combination devices based on allocating special groups of outputs ⋮ Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices
Cites Work
- Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits
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- On summation code properties in functional control circuits
- Checking of combinational circuits basing on modification sum codes
- Necessary and sufficient conditions for the synthesis of completely testable modulo 2 convolution circuits
- Self-checking computer circuits and systems (review)
- Self-checking checkers for balanced codes
- A modified summation code for organizing control of combinatorial circuits
- On codes with summation of data bits in concurrent error detection systems
- A note on error detection codes for asymmetric channels
- Code Design for Dependable Systems
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