High-performance 1-D and 2-D inverse DWT 5/3 filter architectures for efficient hardware implementation

DOI10.1007/s00034-016-0477-2zbMath1371.94717OpenAlexW2565884357MaRDI QIDQ2405843

Vladimir Rajović, Goran Savić, Milan Prokin, Dragana Prokin

Publication date: 26 September 2017

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-016-0477-2

zbMATH Keywords

efficient hardware implementationinverse 5/3 filter architecturesinverse discrete wavelet transform

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

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Cites Work

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• Novel JPEG 2000 compliant DWT and IWT VLSI implementations
• A survey on lifting-based discrete wavelet transform architectures
• Reversible integer-to-integer wavelet transforms for image compression: performance evaluation and analysis
• A theory for multiresolution signal decomposition: the wavelet representation
• High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
• Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT
• VLSI architectures for the discrete wavelet transform
• Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
• Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms

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