Legitimate skew clock routing with buffer insertion

DOI10.1007/S11265-005-4184-7zbMath1103.68429OpenAlexW2077375994MaRDI QIDQ2432131

Xinjie Wei, Meng Zhao, Yici Cai, Xianlong Hong

Publication date: 25 October 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-005-4184-7

zbMATH Keywords

buffer insertionclock routinglegitimate skew

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Zero skew clock routing with minimum wirelength

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