Multidimensional DSP core synthesis for FPGA

DOI10.1007/S11265-006-7271-5zbMath1103.68424OpenAlexW2055860371MaRDI QIDQ2432185

Yanyan Li

Publication date: 25 October 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-006-7271-5

zbMATH Keywords

field programmable gate arrayheterogeneous systemdataflow grapharchitectural synthesisrapid implementationsystem level design.

Mathematics Subject Classification ID

Computer system organization (68M99)

Uses Software

• ESPADON
• Xilinx

Cites Work

• Unnamed Item
• Compilation from Matlab to process networks realized in FPGA
• How rapid is rapid prototyping? Analysis of ESPADON programme results
• High speed FPGA-based implementations of delayed-LMS filters

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