Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform

DOI10.1007/S00034-005-0117-1zbMath1148.65103OpenAlexW2012173436MaRDI QIDQ2465512

Taegeun Park, Junrye Rho, Ju Young Kim

Publication date: 4 January 2008

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-005-0117-1

zbMATH Keywords

VLSI architecturelow complexitybit-serialfolded architecturelattice-based FIR filters

Mathematics Subject Classification ID

Numerical methods for wavelets (65T60) Biochemistry, molecular biology (92C40) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Numerical methods for discrete and fast Fourier transforms (65T50) Complexity and performance of numerical algorithms (65Y20)

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