Stride permutation networks for array processors
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Publication:2477435
DOI10.1007/S11265-006-0031-8zbMath1134.94407OpenAlexW2080054719MaRDI QIDQ2477435
Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Henrik Takala
Publication date: 13 March 2008
Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s11265-006-0031-8
parallel computationinterconnection networkviterbi decodingarray processordata format converterfast fourier transformstride permutation
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Cites Work
- Stride permutation networks for array processors
- One- and two-dimensional constant geometry fast cosine transform algorithms and architectures
- Architecture-oriented regular algorithms for discrete sine and cosine transforms
- Kronecker products and shuffle algebra
- Recursive fast algorithm and the role of the tensor product
- Design of data format converters using two-dimensional register allocation
- Area-efficient architectures for the Viterbi algorithm. I. Theory
- Parallel Processing with the Perfect Shuffle
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