Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

DOI10.1016/j.compeleceng.2005.07.005zbMath1156.68605OpenAlexW2084602893MaRDI QIDQ2489272

Hamid Sarbazi-Azad, A. Masoudnia, S. Boussakta

Publication date: 16 May 2006

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.compeleceng.2005.07.005

zbMATH Keywords

Image processing Performance Wavelet transform FPGA implementation Compression Pipelining Decompression Serial-parallel architecture

Mathematics Subject Classification ID

Computing methodologies for image processing (68U10)

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