Design and implementation of flexible resampling mechanism for high-speed parallel particle filters

DOI10.1007/s11265-006-5919-9zbMath1099.94017OpenAlexW1990583874MaRDI QIDQ2505080

Petar M. Djurić, Sangjin Hong, Shu-Shin Chin, Miodrag Bolic

Publication date: 29 September 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-006-5919-9

zbMATH Keywords

VLSI implementationBayesian signal processingchip implementation

Mathematics Subject Classification ID

Bayesian inference (62F15) Filtering in stochastic control theory (93E11) Bootstrap, jackknife and other resampling methods (62F40) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Sampling theory in information and communication theory (94A20)

Uses Software

• Xilinx

Cites Work

• Unnamed Item
• Resampling algorithms for particle filters: a computational complexity perspective
• Sequential Monte Carlo Methods in Practice
• Rejection Control and Sequential Importance Sampling
• Reconfigurable computing for digital signal processing: A survey

This page was built for publication: Design and implementation of flexible resampling mechanism for high-speed parallel particle filters