Reconfigurable coprocessor for multimedia application domain

DOI10.1007/S11265-006-7512-7zbMath1100.94033OpenAlexW2029891867MaRDI QIDQ2505088

Salvatore M. Carta, Luigi Raffo, Danilo Pani

Publication date: 29 September 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-006-7512-7

zbMATH Keywords

multimediadigital signal processingreconfigurable computingdomain-specific architectures

Mathematics Subject Classification ID

Learning and adaptive systems in artificial intelligence (68T05) Digital control/observation systems (93C62) Circuits, networks (94C99)

Uses Software

• MediaBench

Cites Work

• Reconfigurable computing for digital signal processing: A survey
• A parallel dynamically reconfigurable architecture designed for flexible application-tailored hardware/software systems in future mobile communication
• Unnamed Item

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