A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

DOI10.1007/s11265-005-5271-5zbMath1103.94305OpenAlexW2097783206MaRDI QIDQ2508513

Mohammad M. Mansour, Naresh R. Shanbhag

Publication date: 13 October 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-005-5271-5

zbMATH Keywords

LDPC codesRamanujan graphsturbo-decoding message-passing algorithmVLSI decoder architectures

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30) Applications of graph theory to circuits and networks (94C15) Decoding (94B35)

Uses Software

• AA-LDPC

Cites Work

• Unnamed Item
• Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)

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