Design and implementation of counting networks

DOI10.1007/S00607-013-0360-YzbMath1336.68279OpenAlexW2025754354MaRDI QIDQ2515805

V. Sklyarov, I. Skliarova

Publication date: 6 August 2015

Published in: Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00607-013-0360-y

zbMATH Keywords

FPGApipelineparallel circuitsHamming weight counter/comparatorperformance analysis and design

Mathematics Subject Classification ID

Searching and sorting (68P10) Parallel algorithms in computer science (68W10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Related Items (1)

Structural models of finite-state machines for their implementation on programmable logic devices and systems on chip

Cites Work

• Digital architectures realizing piecewise-linear multivariate functions: Two FPGA implementations
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