On the performance and implementation issues of interleaved single parity check turbo product codes

DOI10.1023/B:VLSI.0000047270.49225.52zbMath1081.94559OpenAlexW1973700615MaRDI QIDQ2574066

Keshab K. Parhi, Yan-Ni Chen

Publication date: 16 November 2005

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/b:vlsi.0000047270.49225.52

zbMATH Keywords

interleaver memoryparallel decoding architecturesign-min algorithmsingle parity check codeturbo product code

Mathematics Subject Classification ID

Other types of codes (94B60) Decoding (94B35)

Uses Software

• LDPC

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