A scalable system architecture for high-throughput turbo-decoders

DOI10.1023/B:VLSI.0000047272.75049.0EzbMath1099.94035OpenAlexW2026640405MaRDI QIDQ2574072

Michael J. Thul, Timo Vogt, Norbert Wehn, Frank Gilbert, Gerd Kreiselmaier

Publication date: 16 November 2005

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/b:vlsi.0000047272.75049.0e

zbMATH Keywords

interleavingVLSI architectureswirelesshigh-throughputparallel decodingTurbo-Decoder

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Analytic circuit theory (94C05) Decoding (94B35)

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