A multiple-valued logic approach to the design and verification of hardware circuits

DOI10.1016/j.jal.2016.01.001zbMath1436.68198arXiv1502.05748OpenAlexW2962748773MaRDI QIDQ266875

Amnon Rosenmann

Publication date: 7 April 2016

Published in: Journal of Applied Logic (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1502.05748

zbMATH Keywords

De Morgan canonical formhardware simulationhardware verificationmultiple-valued logicverification complexity

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07) Many-valued logic (03B50)

Related Items (1)

Matrix expression of finite Boolean-type algebras

Cites Work

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• Analysis of Boolean Functions
• Expressive Completeness for Metric Temporal Logic
• Fuzzy sets
• The Problem of Simplifying Truth Functions
• Computer Aided Verification
• Computer Aided Verification

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