Comments on "The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2/sup k/-1, 2/sub k/, 2/sup k/+1)"

DOI10.1109/82.868470zbMath0980.68149OpenAlexW2093316618MaRDI QIDQ2732956

P. V. Ananda Mohan

Publication date: 2 December 2001

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/82.868470

zbMATH Keywords

reverse convertersresidue arithmetic

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

This page was built for publication: Comments on "The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2/sup k/-1, 2/sub k/, 2/sup k/+1)"