A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation
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Publication:2732968
DOI10.1109/82.899659zbMath0980.68006OpenAlexW4255882396MaRDI QIDQ2732968
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Publication date: 2 December 2001
Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/82.899659
Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)
Related Items (4)
High speed residue to binary converter for the new four-moduli set \(\{2^{2n},2^n+1,2^{n/2}+1,2^{n/2}-1\}\) ⋮ Hierarchical residue number systems with small moduli and simple converters ⋮ An efficient RNS parity checker for moduli set \(\{2^n - 1, 2^n + 1, 2^{2n} + 1\}\) and its applications ⋮ Efficient CRT-based residue-to-binary converter for the arbitrary moduli set
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