An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions

DOI10.1016/S0167-9260(00)00011-0zbMath0969.68029WikidataQ127391551 ScholiaQ127391551MaRDI QIDQ2734609

Dominique Lavenier

Publication date: 20 August 2001

Published in: Integration (Search for Journal in Brave)

zbMATH Keywords

FPGAsystolic arraypseudo-random bit generatorGoldbach partitions

Mathematics Subject Classification ID

Computer system organization (68M99)

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