A bit-interleaved systolic architecture for a high-speed RSA system

DOI10.1016/S0167-9260(01)00017-7zbMath0983.68258OpenAlexW2002761757MaRDI QIDQ2778434

N. K. Moshopoulos, K. Z. Pekmestzi

Publication date: 3 March 2002

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-9260(01)00017-7

zbMATH Keywords

RSAMontgomerysquare and multiplysystolic circuit

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

This page was built for publication: A bit-interleaved systolic architecture for a high-speed RSA system