QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations

DOI10.1007/978-3-319-29814-6_15zbMath1384.94106OpenAlexW2485106005MaRDI QIDQ2801768

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Publication date: 21 April 2016

Published in: Information and Communications Security (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-29814-6_15

zbMATH Keywords

high performanceFPGApower analysisdual-rail precharge logic (DPL)quadruple-rail

Mathematics Subject Classification ID

Cryptography (94A60)

Cites Work

• Unnamed Item
• An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation
• Cryptographic Hardware and Embedded Systems - CHES 2004
• Advances in Cryptology - CRYPTO 2003

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