QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations
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Publication:2801768
DOI10.1007/978-3-319-29814-6_15zbMath1384.94106OpenAlexW2485106005MaRDI QIDQ2801768
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Publication date: 21 April 2016
Published in: Information and Communications Security (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-319-29814-6_15
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