Optimized parity preserving quantum reversible full adder/subtractor

DOI10.1142/S0219749916500192zbMath1346.81027OpenAlexW2463481363MaRDI QIDQ2816407

Majid Haghparast, Ali Bolhassani

Publication date: 22 August 2016

Published in: International Journal of Quantum Information (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1142/s0219749916500192

zbMATH Keywords

quantum computingquantum informationreversible logicfull adder/subtractorparity preservingBCD adderbinary to BCD converterNANO-metric circuits

Mathematics Subject Classification ID

Quantum computation (81P68)

Related Items (4)

The quantum accelerated PointNet algorithm ⋮ Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate ⋮ Quaternary quantum/reversible half-adder, full-adder, parallel adder and parallel adder/subtractor circuits ⋮ Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder

Cites Work

• Novel designs of nanometric parity preserving reversible compressor
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