Verification of Asynchronous Circuits using Timed Automata

DOI10.1016/S1571-0661(04)80468-7zbMath1270.68164MaRDI QIDQ2842571

Sergio Yovine, Marius Bozga, Hou Jianmin, Oded Maler

Publication date: 15 August 2013

Published in: Electronic Notes in Theoretical Computer Science (Search for Journal in Brave)

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (2)

Model Checking Real-Time Systems ⋮ Timed verification of the generic architecture of a memory circuit using parametric timed automata

Uses Software

• Kronos
• Uppaal
• Petrify

Cites Work

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• A theory of timed automata
• Uppaal in a nutshell
• Timing verification by successive approximation
• Generalized ternary simulation of sequential circuits

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