Modeling of jitter in bang‐bang clock and data recovery circuits

DOI10.1108/03321641311309067zbMath1328.94108OpenAlexW2059564045MaRDI QIDQ2842763

Seyed Saleh Ghoreishi, Habib Adrang

Publication date: 16 August 2013

Published in: COMPEL - The international journal for computation and mathematics in electrical and electronic engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1108/03321641311309067

zbMATH Keywords

circuitstelecommunication systemsbang-bang phase detector (BBPD)clock and data recovery (CDR)jitter transfer and jitter tolerance

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Uses Software

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