Performance of a new split digital phase lock loop in additive wideband Gaussian noise

DOI10.1002/acs.2385zbMath1282.93234OpenAlexW1895016028WikidataQ59713270 ScholiaQ59713270MaRDI QIDQ2874388

Ujjwal Maulik, Baidyanath Biswas, Surjadeep Sarkar

Publication date: 30 January 2014

Published in: International Journal of Adaptive Control and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/acs.2385

zbMATH Keywords

field programmable gate array (FPGA)BERsignal-to-noise ratio (SNR)DCO with phase modulationdigital phase lock loop (DPLL)digitally controlled oscillator (DCO)noise bandwidthsplit-loop DPLL

Mathematics Subject Classification ID

Stochastic systems in control theory (general) (93E03)

Uses Software

• Matlab
• Simulink
• Xilinx
• Spartan 3E Starter Kit

Cites Work

• Unnamed Item

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