VLSI layouts of complete graphs and star graphs

DOI10.1016/S0020-0190(98)00133-1zbMath1339.68216OpenAlexW2155555720MaRDI QIDQ293402

Chi-Hsiang Yeh, Behrooz Parhami

Publication date: 9 June 2016

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: http://www.sciencedirect.com/science/article/pii/S0020019098001331?np=y

zbMATH Keywords

complete graphsparallel processingVLSI layoutstar graphs

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10)

Related Items (3)

On the problem of determining which \((n, k)\)-star graphs are Cayley graphs ⋮ Two models of two-dimensional bandwidth problems ⋮ Unnamed Item

Cites Work

• Unnamed Item
• Unnamed Item
• On VLSI layouts of the star graph and related networks
• A class of recursive interconnection networks: architectural characteristics and hardware cost
• On the genus of star graphs
• Transposition networks as a class of fault-tolerant robust networks

This page was built for publication: VLSI layouts of complete graphs and star graphs