Optimization approaches for designing quantum reversible arithmetic logic unit

DOI10.1007/S10773-015-2782-0zbMath1338.81133OpenAlexW1276671512MaRDI QIDQ293885

Ali Bolhassani, Majid Haghparast

Publication date: 9 June 2016

Published in: International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10773-015-2782-0

zbMATH Keywords

quantum computationquantum gatesreversible logiclow power designquantum computerquantum costreversible ALU

Mathematics Subject Classification ID

Quantum computation (81P68)

Related Items (5)

Novel quaternary quantum decoder, multiplexer and demultiplexer circuits ⋮ On design of parity preserving reversible adder circuits ⋮ A fault-tolerant and scalable column-wise reversible quantum multiplier with a reduced size ⋮ Optimized 4-bit quantum reversible arithmetic logic unit ⋮ Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit

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• MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
• Towards a Design Flow for Reversible Logic
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation

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