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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors - MaRDI portal

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

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Publication:2982090

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DOI10.1109/TC.2014.2378291zbMath1360.68062MaRDI QIDQ2982090

Sung Woo Chung, Farinaz Koushanfar, Joonho Kong

Publication date: 16 May 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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