Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

DOI10.1109/TC.2015.2490058zbMath1360.68240OpenAlexW2345221967MaRDI QIDQ2985347

Chandrasekharan Tirumurti, Martin Omaña, Rajesh Galivanche, Daniele Rossi, Edda Beniamino, Cecilia Metra

Publication date: 16 May 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2015.2490058

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

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