Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation

DOI10.1109/TC.2015.2479617zbMath1360.68968MaRDI QIDQ2985389

Arash Reyhani-Masoleh, Dipanwita Gangopadhyay

Publication date: 16 May 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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