Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

DOI10.1109/TC.2016.2584067zbMATH Open1364.68046OpenAlexW2473178953MaRDI QIDQ2989510

Hossam A. H. Fahmy, Ahmed A. Wahba

Publication date: 8 June 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2016.2584067

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Related Items (2)

Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support ⋮ Area-Efficient Multipliers Based on Multiple-Radix Representations

This page was built for publication: Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2989510)