Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy

DOI10.1007/3-540-45653-8_3zbMath1275.68096OpenAlexW1528291435MaRDI QIDQ2996152

Klaus Schneider

Publication date: 6 May 2011

Published in: Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/3-540-45653-8_3

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44)

Related Items (5)

Bounded model checking of infinite state systems ⋮ Graph Games and Reactive Synthesis ⋮ Assumption-based runtime verification ⋮ From LTL to Symbolically Represented Deterministic Automata ⋮ More efficient on-the-fly LTL verification with Tarjan's algorithm

Uses Software

• Cadence SMV
• LTL2BA

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