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GATE RESIZING TO REDUCE POWER CONSUMPTION - MaRDI portal

GATE RESIZING TO REDUCE POWER CONSUMPTION

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Publication:3021961

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DOI10.1142/S0129054102001187zbMATH Open1066.94024OpenAlexW2062986585MaRDI QIDQ3021961

Edward Y. C. Cheng, Sartaj Sahni

Publication date: 22 June 2005

Published in: International Journal of Foundations of Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1142/s0129054102001187

zbMATH Keywords

power consumption timing constraints gate resizing

Mathematics Subject Classification ID

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