One-dimensional logic gate assignment and interval graphs

DOI10.1109/TCS.1979.1084695zbMath0414.94052OpenAlexW2089651609WikidataQ59445248 ScholiaQ59445248MaRDI QIDQ3050329

Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa, Tatsuo Ohtsuki, Hajimu Mori

Publication date: 1979

Published in: IEEE Transactions on Circuits and Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcs.1979.1084695

zbMATH Keywords

interval graphNp-completealgorithm for gate sequencingdesign of one-dimensional logic gate arrays

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Applications of graph theory to circuits and networks (94C15)

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