Verifying Deadlock-Freedom of Communication Fabrics

DOI10.1007/978-3-642-18275-4_16zbMath1317.68115OpenAlexW3139271637MaRDI QIDQ3075484

Satrajit Chatterjee, Michael Kishinevsky, Alexander Gotmanov

Publication date: 15 February 2011

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-18275-4_16

zbMATH Keywords

livenessformal verificationdeadlockscommunication fabricshigh-level modelsmicroarchitecturenetworks-on-chip

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (1)

Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics

Uses Software

• ABC

Cites Work

• Reachability Problems in Piecewise FIFO Systems
• Proving that non-blocking algorithms don't block
• Correct Hardware Design and Verification Methods

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