A dual basis bit-serial systolic multiplier for GF(2 )

DOI10.1016/0167-9260(95)00007-3zbMATH Open0875.68554OpenAlexW2054183086WikidataQ127846512 ScholiaQ127846512MaRDI QIDQ3122545

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Publication date: 28 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(95)00007-3

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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