Mapping full‐systolic arrays for matrix product on XILINX's XC4000(E,EX) FPGAs

DOI10.1108/03321640210410751zbMath1001.68918OpenAlexW2020013925MaRDI QIDQ3146405

S. Titri, Abdelkrim Kamel Oudjida, M. Hamerhain

Publication date: 11 September 2002

Published in: COMPEL - The international journal for computation and mathematics in electrical and electronic engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1108/03321640210410751

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Unnamed Item
• An even faster systolic array for matrix multiplication
• A two-layered mesh array for matrix multiplication
• The Design of Optimal Systolic Arrays
• A family of new efficient arrays for matrix multiplication

This page was built for publication: Mapping full‐systolic arrays for matrix product on XILINX's XC4000(E,EX) FPGAs