Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

DOI10.1007/978-3-642-23951-9_32zbMath1285.94068OpenAlexW154446972MaRDI QIDQ3172988

Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol

Publication date: 7 October 2011

Published in: Cryptographic Hardware and Embedded Systems – CHES 2011 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-23951-9_32

zbMATH Keywords

FPGAbenchmarkinghash functionsSHA-3hardware

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

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Lightweight Implementations of SHA-3 Candidates on FPGAs ⋮ Hardware optimizations of stream cipher rabbit

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