Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition

DOI10.1109/TPAMI.1984.4767522zbMath0529.68061WikidataQ52695228 ScholiaQ52695228MaRDI QIDQ3311705

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Publication date: 1984

Published in: IEEE Transactions on Pattern Analysis and Machine Intelligence (Search for Journal in Brave)

zbMATH Keywords

Earley's algorithmsyntactic pattern recognitionVLSI arrayerror-correcting recognitionparallel CFL parsingparallel CFL recognitionparsing matrix

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10) Theory of compilers and interpreters (68N20) Theory of operating systems (68N25)

Related Items (11)

Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture ⋮ A parallel parsing algorithm for arbitrary context-free grammars ⋮ VLSI architectures for string matching and pattern matching ⋮ Efficient simulations of simple models of parallel computation by time- bounded ATMs and space-bounded TMs ⋮ Parallel \(LL\) parsing ⋮ parallel parsing from recurrence equations ⋮ Efficient reconfigurable embedded parsers ⋮ An NC algorithm for recognizing tree adjoining languages ⋮ Systolic parsing of context-free languages ⋮ An efficient all-parses systolic algorithm for general context-free parsing ⋮ Efficient error-correcting parsing for (attributed and stochastic) tree grammars

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