Dynamically Restructurable Fault-Tolerant Processor Network Architectures

DOI10.1109/TC.1985.1676583zbMath0558.94019OpenAlexW1967281838MaRDI QIDQ3347791

Dhiraj K. Pradhan

Publication date: 1985

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1985.1676583

zbMATH Keywords

binary treemodular networkdistributed systemcircuit switchingparallel systempacket switchingdynamic processingfault- tolerant multiprocessor networksself-routing

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15) Theory of operating systems (68N25) Theory of software (68N99)

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