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HIGH SPEED SYNCHRONIZATION FOR A STATICALLY SCHEDULED SUPERSCALAR PROCESSOR - MaRDI portal

HIGH SPEED SYNCHRONIZATION FOR A STATICALLY SCHEDULED SUPERSCALAR PROCESSOR

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Publication:3357519

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DOI10.1142/S012905339100005XzbMath0731.68017OpenAlexW2010045045MaRDI QIDQ3357519

Takaya Arita, Masahiro Sowa

Publication date: 1991

Published in: International Journal of High Speed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1142/s012905339100005x

zbMATH Keywords

synchronization VLIW parallel control flow model Superscalar processors token counters

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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