A class of unidirectional bit serial systolic architectures for multiplicative inversion and division over GF(2/sup m/)

DOI10.1109/TC.2005.35zbMath1127.68336OpenAlexW2110711133MaRDI QIDQ3417013

Amir K. Daneshbeh, M. Anwarul Hasan

Publication date: 9 January 2007

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2005.35

zbMATH Keywords

systolic arrays

Mathematics Subject Classification ID

Nonnumerical algorithms (68W05) Mathematical problems of computer architecture (68M07)

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