Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

DOI10.1109/12.888044zbMath1314.94122OpenAlexW2150032667MaRDI QIDQ3417048

Yervant Zorian, Dimitris Gizopoulos, Antonis Paschalis, Mihalis Psarakis

Publication date: 9 January 2007

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.888044

zbMATH Keywords

iterative logic arrays

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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