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Design and implementation of a high-speed reconfigurable cipher chip - MaRDI portal

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Design and implementation of a high-speed reconfigurable cipher chip

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Publication:3423654

DOI10.1016/S1004-4132(07)60003-6zbMATH Open1130.94339OpenAlexW1572426943WikidataQ123138959 ScholiaQ123138959MaRDI QIDQ3423654

Author name not available (Why is that?)

Publication date: 14 February 2007

Published in: (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s1004-4132(07)60003-6



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