Correlation bounds and \#SAT algorithms for small linear-size circuits
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Publication:344759
DOI10.1016/j.tcs.2016.05.005zbMath1353.68113OpenAlexW1625693084MaRDI QIDQ344759
Ruiwen Chen, Valentine Kabanets
Publication date: 24 November 2016
Published in: Theoretical Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.tcs.2016.05.005
Related Items
Gate elimination: circuit size lower bounds and \#SAT upper bounds ⋮ Bounded depth circuits with weighted symmetric gates: satisfiability, lower bounds and compression
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