Formal Design of Asynchronous Fault Detection and Identification Components using Temporal Epistemic Logic

DOI10.2168/LMCS-11(4:4)2015zbMath1448.68289arXiv1506.04871OpenAlexW2950420876WikidataQ62041120 ScholiaQ62041120MaRDI QIDQ3449766

Stefano Tonetta, Marco Gario, Marco Bozzano, Alessandro Cimatti

Publication date: 5 November 2015

Published in: Logical Methods in Computer Science (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1506.04871

zbMATH Keywords

model checkingtemporal epistemic logicfault detection and identificationdiagnoser synthesis

Mathematics Subject Classification ID

Logics of knowledge and belief (including belief change) (03B42) Specification and verification (program logics, model checking, etc.) (68Q60) Reliability, testing and fault tolerance of networks and computer systems (68M15) Temporal logic (03B44)

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