Essential Traffic Parameters for Shared Memory Switch Performance
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Publication:3460707
DOI10.1007/978-3-319-25258-2_5zbMath1471.68031OpenAlexW1756212337WikidataQ58452123 ScholiaQ58452123MaRDI QIDQ3460707
Alexander V. Sirotkin, Sergey I. Nikolenko, Kirill Kogan, Patrick Eugster, Alexander Kesselman
Publication date: 8 January 2016
Published in: Structural Information and Communication Complexity (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-319-25258-2_5
Network design and communication in computer systems (68M10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Distributed systems (68M14)
Related Items (4)
The impact of processing order on performance: a taxonomy of semi-FIFO policies ⋮ Competitive buffer management for multi-queue switches in QoS networks using packet buffering algorithms ⋮ Online packet scheduling for CIOQ and buffered crossbar switches ⋮ Admission control in shared memory switches
Cites Work
- Lower and upper bounds on FIFO buffer management in QoS switches
- Harmonic buffer management policy for shared memory switches
- Maximizing throughput in multi-queue switches
- Improved competitive performance bounds for CIOQ switches
- An improved algorithm for CIOQ switches
- Competitive queue policies for differentiated services
- Buffer Overflow Management in QoS Switches
- FIFO Queueing Policies for Packets with Heterogeneous Processing
- Competitive buffer management for shared-memory switches
- Optimal smoothing schedules for real-time streams (extended abstract)
- On the Performance of Greedy Algorithms in Packet Buffering
- Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing
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