Implementation of the AES-128 on Virtex-5 FPGAs

DOI10.1007/978-3-540-68164-9_2zbMath1142.94335OpenAlexW1698058651WikidataQ58765281 ScholiaQ58765281MaRDI QIDQ3506369

Jean-Jacques Quisquater, Gael Rouvroy, Pascal Pellegrin, Philippe Bulens, François-Xavier Standaert

Publication date: 13 June 2008

Published in: Progress in Cryptology – AFRICACRYPT 2008 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-68164-9_2

Mathematics Subject Classification ID

Cryptography (94A60)

Related Items (2)

Spin me right round rotational symmetry for FPGA-specific AES: extended version ⋮ Resource efficient implementation of \(T\)-boxes in AES on virtex-5 FPGA

Cites Work

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• AES on FPGA from the Fastest to the Smallest
• A Very Compact S-Box for AES
• Cryptographic Hardware and Embedded Systems - CHES 2004

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