Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces

DOI10.1007/978-3-540-75596-8_10zbMath1141.68476OpenAlexW2134451579MaRDI QIDQ3510791

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Publication date: 3 July 2008

Published in: Automated Technology for Verification and Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-75596-8_10

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• Unnamed Item
• Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
• Temporal Logic Verification Using Simulation
• Automated Technology for Verification and Analysis
• Formal Methods in Computer-Aided Design
• Hybrid Systems: Computation and Control
• On hybrid Petri nets

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