3-Valued Circuit SAT for STE with Automatic Refinement

DOI10.1007/978-3-540-75596-8_32zbMath1141.68467OpenAlexW1488816276MaRDI QIDQ3510816

Avi Yadgar, Assaf Schuster, Orna Grumberg

Publication date: 3 July 2008

Published in: Automated Technology for Verification and Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-75596-8_32

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (2)

Abstraction and Abstraction Refinement ⋮ Efficient Automatic STE Refinement Using Responsibility

Uses Software

• SATO

Cites Work

• Counterexample-guided abstraction refinement for symbolic model checking
• Hybrid BDD and All-SAT Method for Model Checking
• SATO: An efficient propositional prover
• Computer Aided Verification
• A Computing Procedure for Quantification Theory
• A machine program for theorem-proving
• Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation
• Unnamed Item

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