Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

DOI10.1007/11867340_9zbMath1141.68460OpenAlexW1567141323MaRDI QIDQ3511227

Remy Chevallier, Weiwen Xu, Emmanuelle Encrenaz-Tiphene, Laurent Fribourg

Publication date: 8 July 2008

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11867340_9

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

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Timed verification of the generic architecture of a memory circuit using parametric timed automata ⋮ Time Separation of Events: An Inverse Method

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