Temporal Logic Verification Using Simulation

DOI10.1007/11867340_13zbMath1141.68463OpenAlexW2120953717MaRDI QIDQ3511234

Antoine Girard, Georgios E. Fainekos, George J. Pappas

Publication date: 8 July 2008

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://repository.upenn.edu/cgi/viewcontent.cgi?article=1296&context=cis_papers

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44)

Related Items (8)

Verification of Hybrid Systems ⋮ Temporal Logic Verification for Delay Differential Equations ⋮ Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces ⋮ Approximate bisimulation: a bridge between computer science and control theory ⋮ A survey of challenges for runtime verification from advanced application domains (beyond software) ⋮ Analog property checkers: a DDR2 case study ⋮ Robustness of temporal logic specifications for continuous-time signals ⋮ Monitoring bounded LTL properties using interval analysis

Uses Software

• PHAVer

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